The present invention is related to digital clock circuits, and more particularly to a digital delay lock loop (digital DLL) circuit for generating synchronized signals to a reference signal.
Digital DLL circuits have been commonly used for the purpose of generating a signal in a preferred phase relationship relative to another signal. A digital DLL adjusts its own internal clock to bring it into alignment with some external reference clock. The phase relationship between the reference clock and the internal clock is then referred to as being locked. An essential part of a digital DLL is a phase detector, which generates a control signal based on the deviation of the internal clock with reference to the reference clock. This control signal is then used to correct the phase deviation.
A phase detector circuit is used in a control loop in which a certain fixedly predetermined phase offset is generated between the internal and reference clocks. This means that a digital DLL circuit can only generate and keep a constant phase difference between the internal and reference clock signals corresponding to the phase offset. This also means that the digital DLL circuit can only synchronize the reference and internal clock signals within in this phase offset uncertainty. That is, the resolution of the synchronization of the reference and internal clocks depends on the phase offset. Typically, in a digital DLL circuit the two signals can only be synchronized to within the delay through one minimum delay element. Therefore, the resolution of synchronization in digital DLL circuits ends up being slightly higher than plus or minus one minimum delay element.
However, such a resolution based on the phase offset or delay generated using NAND gates in a digital DLL circuit for synchronization of the reference and internal clocks is still not desirable. As clock speeds continue to increase, timing tolerances between reference and internal clocks have become increasingly severe. The problem is exacerbated by the increasing complexity in contemporary integrated circuits, which require a large number of events to be accurately timed with respect to each other. The problem is further exacerbated by varying silicon delays due to variations in the process parameters during IC fabrication of semiconductor chips. These timing constraints threaten to create a significant roadblock to increasing the operating speeds of many conventional integrated circuits.
In addition, the phase offset generated by digital DLL circuits during synchronization of the internal and reference clocks produces undesirable phase jitter when the reference and internal clocks are within the window of a phase offset. Jitter is defined as abrupt, spurious variations in the phase of successive pulses as referenced to the phase of a continuous oscillator, causing deleterious variations in the output frequency. Edge sensitive circuits using flip-flops are generally sensitive to jitter and the circuits may be perturbed for many cycles after a jitter event. Therefore the phase detector circuit may have to be turned off to avoid negative effects of jitter. Once the phase detector circuit is turned off it can no longer adjust for temperature and voltage drifts, which can result in an increased phase offset as the internal clock can drift from the reference.
For the reasons stated above, and for reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a digital DLL circuit including a phase detector circuit that can generate an internal clock signal with a reduced phase offset with respect to a reference clock signal. Further, there is a need in the art for a digital DLL circuit with a low phase offset jitter in response to phase offset and when the internal clock is within the window of the reference clock.
The above-mentioned shortcomings, disadvantages and problems are addressed by the present invention, which will be understood by reading and studying the following specification.
In one aspect of the present invention, a system and method is described for synchronizing a system clock signal with a reference clock signal having a reduced phase offset. This is accomplished by generating delayed system and delayed reference clock signals by using the system and reference clock signals. The generated delayed clock signals are then monitored to determine the order of arrival of the raising and falling edges of the delayed clock signals. The system clock signal is then compensated as a function of the order of arrival of the delayed clock signals to substantially synchronize the system clock signal with the reference clock signal.
According to one aspect of the present invention, a method of synchronizing a system clock signal with a reference clock signal includes generating a delayed reference clock signal having a first minimum time delay using a reference clock signal. In addition, a delayed system clock signal having second minimum time delay is generated using a system clock signal. The clock signals include first and second edges in each clock cycle. The second minimum time delay is about half the first minimum time delay. A first signal is then generated based on the order of arrival of the first and second edges of the reference clock signal with respect to the first and second edges of the delayed system clock signal in each clock cycle. In addition, a second signal is then generated based on the order of arrival of the first and second edges of the delayed reference clock signal with respect to the first and second edges of the delayed system clock signal in each clock cycle. A logic signal is then generated based on the generated first and second signals. The system clock signal is then compensated to substantially synchronize the system clock signal with the reference clock signal as a function of the received logic signal.
Another aspect of the present invention provides a digital delay lock loop circuit for synchronizing a system clock signal with a reference clock signal, includes a delayed reference clock circuit, a delayed system clock circuit, a phase detector circuit, and a compensation circuit. The compensation circuit further includes a first edge detector circuit, a second edge detector circuit, and a logic circuit. The delayed reference clock circuit receives a reference clock signal and generates a delayed reference clock signal having a first minimum time delay with respect to the reference clock signal. The delayed system clock circuit receives a system clock signal and generates a delayed system clock signal having a second minimum time delay, the second minimum time delay being one half the first minimum time delay. The first edge detector circuit receives the reference and delayed system clock signals and generates a first signal based on the order of arrival of the first and second edges of the reference and delayed system clock signal in each clock cycle. The second edge detector circuit receives the delayed reference and system clock signals and generates a second signal based on the order of arrival of the first and second edges of the delayed reference and system clock signals in the clock cycle. The logic circuit then receives the first and second signals from the first and second edge detector circuits and outputs a logic signal as a function of the received first and second signals. The compensation circuit then receives the system clock signal and the logic signal and substantially synchronizes the received system clock signal to the reference clock signal by compensating the system clock signal as a function of the received logic signal.
The present invention describes systems, methods, and computer-readable media of varying scope. In addition to the aspects and advantages of the present invention described in this summary, further aspects and advantages of the invention will become apparent by reference to the drawings and by reading the detailed description that follows.